This disclosure relates to integrated circuits and to data processing within such integrated circuits.
Some integrated circuit devices, for example so-called “systems on chip” (SoC) devices, provide data processing functions on a single integrated circuit substrate along with a first data processing element acting as an interface, sometimes referred to as a physical interface or PHY, to one or more external memory devices. A second data processing element, for example a memory controller (MC), is provided on the substrate to communicate with the PHY.
In some examples, at least some functions of the PHY operate at a higher clock speed than the clock speed by which the MC operates. An example arrangement relates to the use of so-called double data rate (DDR) memory such as DDR synchronous dynamic random access memory (DDR SDRAM). Here, the expression “DDR” is used in a generic manner to refer to variants of the DDR arrangement, including (without limitation) the so-called DDR2, DDR3 and other variants.
DDR memory communicates data at twice the rate of an equivalent single data rate (SDR) memory device running at the same clock speed.
In terms of the PHY, the use of DDR memory involves the PHY communicating data, address and/or control signals with the MC at a particular clock speed and a data width (number of bits handled in parallel) of N, but communicating such signals with the DDR memory at twice that clock speed but a data width of N/2.
Accordingly, at least parts of the PHY require a clock signal at twice the clock frequency of the clock signal required by at least parts of the MC.